The present invention relates to a method for batch fabricating stacked semiconductor diodes, and more particularly to the fabrication of stacked P-I-N or P-N diodes for high power/low loss applications.
Typically, multiple diodes are stacked in series to achieve higher power handling capability. This increase occurs because the breakdown voltage of the stacked diodes is essentially equal to the sum of the breakdown voltages of the individual diodes which comprise it. Furthermore, if the stack is comprised of P-I-N diodes, the stack will exhibit a resistive loss (or forward resistance) lower than that of an equivalent individual diode. This occurs because the total thickness of the I layer is distributed over a plurality of diodes in the stack rather than being entirely within a single diode.
For P-I-N diodes the forward resistance is the sum of the plasma resistance, diffusion resistance, contact resistance, and series resistance of the contact layers. However, since the magnitude of the plasma resistance is far more significant than the other resistance components, (particularly at frequencies above 100 MHz), the forward resistance can be approximated by merely considering the plasma resistance term alone. This yields ##EQU1## where R.sub.F is the forward resistance, R.sub.p is the plasma resistance, d is the I layer thickness, I.sub.F is the forward current, .mu. is the sum of the electron and hole mobilities, and .tau. is the effective carrier lifetime. In the stacked diode, the total R.sub.F is the sum of the R.sub.F 's of the individual diodes in the stack. Since the R.sub.F of a diode is proportional to the square of its I layer thickness, the R.sub.F of a single diode of I layer thickness X is greater than the R.sub.F of a stacked diode comprised of N diodes of I layer thickness X/N.
Techniques for fabricating both individual and stacked diodes are known and used in the semiconductor industry. However, these existing techniques create difficulties when adapted to high power/low loss applications. Producing a stacked configuration from individually generated diodes requires that a bonding operation be performed on the individual diodes. This creates the need for a handling procedure to manipulate the typically small diodes, a potentially costly and inefficient operation.
To avoid these handling problems associated with a bonding operation performed on individual diodes, processes have been developed which include stacking the diodes while they are in wafer form. These techniques generally comprise the steps of semiconductor wafer doping and metallization, laminating the desired number of wafers together, pattern generating the diodes on the exposed wafer surfaces, dicing the wafer into laminated stacks, and performing a finishing operation on the diced surfaces of the stacks. The dicing of the laminated wafer is generally accomplished by mechanical cutting, since the laminations typically include layers of metal as well as semiconductor material. The mechanical cutting operation, however, causes damage to the cut semiconductor surfaces, and necessitates the performance of a surface finishing step. This surface finishing is typically performed by a chemical etch, and can be performed, for example, as described in U.S. Pat. No. 3,929,531, issued Dec. 30, 1975 to H. Hattori and Y. Takayama.
However, in the case of stacked diodes which are comprised of two P-I-N diodes, and are to be used in high power/low loss applications, this manufacturing technique is unsatisfactory. For high power/low loss applications, the damage caused to the semiconductor surfaces during the cutting operation cannot be adequately rectified by subsequent chemical surface finishing, as taught by the prior art. The present invention describes an efficient method for fabricating stacked diodes comprised of two diodes.